Memory devices and logic arrays have matrices of cells. In memory arrays the cells hold data; in logic arrays the cells include elements for AND and OR cells. In either array, the cells provide an output to an output line. The output line is connected to a sense amplifier. The magnitude of the signal placed on the output line is low. The output signal has to be sensed and amplified before it can be used to drive an output circuit, such as a display, or before it is put on a bus for transmission to another device.
Memory and logic arrays are normally constructed with either a unipolar (MOS) or bipolar process. Recently such arrays have been constructed with a BIMOS or BICMOS process. In order to increase the speed of such arrays, others have used processes that include steps for fabricating Schottky diodes and Schottky transistors. A well known advantage of such transistors is their property for preventing a bipolar logic transistor from entering saturation. Saturation will slow the switching speed of such transistors.
Certain processes are not compatible with the formation of Schottky devices. In particular, a BICMOS process developed and used by Texas Instruments, Inc., the assignee of this patent, is not compatible with Schottky device formation. Rather than alter the process, it would be desirable to have another solution for obtaining the beneficial effects of non-saturating bipolar transistor without the use of Schottky devices. Such a solution would be especially useful in a memory or logic array that uses bipolar transistor as sense amplifiers to read the output of an array.